The present invention relates to a method and system for analyzing defects in electronic circuits produced by forming electronic circuit patterns on a substrate. More specifically, the present invention relates to defect analysis technology for accurately evaluating the electronic criticality of defects generated in intermediate processes and performing analysis thereof with priority being given to defects having a high electronic criticality. In particular, the present invention provides a technology suitable for use in electronic circuit production, where production takes place through multiple production processes, such as in semiconductor devices.
Semiconductor device production involves hundreds of production processes and requires dozens of days from the start of wafer processing to completion. The object of each of the production processes is to provide proper electronic operation at the time of completion. For this reason, it is important to discover, during intermediate processes, critical defects off the type that will lead to electronic faults upon completion and to prevent these defects from being generated.
Japanese laid-open patent publication number Hei 11-176899 (the first conventional technology) describes a defect warning method and a defect warning system. When a testing process performed at the end of the wafer production process is reached, a consistency check is performed between coordinates of defects detected in inspections performed at intermediate processes and coordinates of faults detected in the testing process. The process and location of the generation of critical defects leading to faults is determined in the testing process and an evaluation value is calculated. A warning is issued if the evaluation value exceeds a predetermined threshold value.
Japanese laid-open patent publication number Hei 8-21803 (the second conventional technology) describes a defect type evaluation device. Defect images are captured at an intermediate process, and defect information extracted from the defect images are provided as an input to a neural processing unit. Defect types are identified from the output. In this conventional technology, defects representative of different defect types are used as samples for preliminary training. The samples are prepared manually through observation and classification of defect images. Image characteristics extracted from the defect images through image processing are used for the defect information provided as an input to the neural processing unit.
In the first conventional technology described above, critical defects cannot be evaluated until the semiconductor device is completed and the testing process is reached. As a result, there is a delay between the time when a defect is generated and the time when further defects can be measured, making production of faulty products unavoidable. If critical defects are repeatedly generated at the same place on wafers, the coordinates obtained from inspections at intermediate processes can be used to detect generation of critical defects. However, this applies only to these restricted cases.
In the second conventional technology, defects can be classified in intermediate processes into categories based on similar image characteristics. However, accurate classification of critical defects and non-critical defects is difficult. To accurately classify critical defects, the accurate preparation of samples used for training is important. However, preparing accurate critical defect samples for different types of defects generated in the production process through manual observation and classification is difficult. For example, with adhesion of contaminants on an electronic circuit pattern, not all contaminants will lead to a critical defect. The probability that a contaminant will lead to a short-circuit defect will vary greatly depending on whether the contaminant is formed from a conductive material or a non-conductive material. Also, the probability that a containment will lead to a short-circuit defect will vary depending on the relation between the height of the containment and the thickness of the film forming the electronic circuit pattern. Information relating to the material and height of contaminants is difficult to identify through manual observation of defect images.